A Systematic Approach to Mitigate Parasitics for Wide-Band High Isolation CMOS SPDT Switch

This paper presents an SPDT switch with series-shunt topology implemented in a 180nm triple-well CMOS process, utilising a switched resistive body floating technique to achieve high isolation. The utilisation of FETs with triple-well provides better performance in terms of noise, isolation, and wideband frequencies from 100MHz to 5GHz. After parasitic extraction (PEX), achieving specifications is often considered a challenge. Therefore, various layout techniques are implemented to mitigate the effects of post-layout parasitics. The proposed design accomplishes an insertion loss of 0.956dB, return loss of 11.7dB, isolation better than 45dB, and output P<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</inf> of 10.5dBm after PEX at 2.6GHz.