Test Generation Algorithms for Computer Hardware Description Languages
Алгоритмы генерации тестов для языков описания компьютерной аппаратуры
1982-07-01
SCID: 54.1/8aa6f45r
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D-algorithmD-propagationhardware description languagesstuck-at faultstest generation
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Abstract (AI)
This paper proposes an extension of the D-algorithm to functions described in computer hardware description languages. The proposed extension is applicable to both procedural and nonprocedural languages. Methods of D-propagation through the basic constructs of these languages and test generation for circuits containing functions described in CHDL's are discussed. The fault modes considered are function variables stuck at 0 or 1, control faults, and function faults with user-specified faulty behaviors.
Key Findings
1
It defines D-propagation methods through basic language constructs for test generation in circuits containing CHDL functions.
2
The approach addresses variables stuck at 0 or 1, control faults, and function faults with user-specified faulty behaviors.
3
The extension applies to both procedural and nonprocedural hardware description languages.
4
The paper extends the D-algorithm to generate tests for functions described in computer hardware description languages.
Research Object
functions and circuits described in computer hardware description languages (CHDLs)
Research Subject
test generation for stuck-at, control, and user-specified function faults using an extended D-algorithm
Publication Details
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1982-07-01
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