Implementation of RISC-V Processor along with Radix-2 Booth Multiplier Using Verilog

This paper presents the integration of a Radix-2 Booth multiplier within a RISC-V soft-core processor architecture, implemented in Verilog. Unlike traditional approaches that treat the multiplier as an isolated module, our design embeds the Booth multiplier directly into the execution stage of the pipeline, optimizing signed multiplications with reduced cycle latency. We introduce a control-path optimization technique for conditional activation of the multiplier unit, minimizing dynamic power consumption. Verified on FPGA, our implementation demonstrates superior performance compared to multiple open-source RISC-V variants, achieving a delay of 5.95 ns, power consumption of 0.103 µW, and area efficiency with 1123 LUTs and 426 registers. This study highlights the advantages of a tightly coupled Booth multiplier in lightweight, pipelined RISC-V architectures, enhancing performance for edge computing and embedded applications.