Software Implementation of Fast List Decoder for PAC Codes
Программная реализация быстрого списочного декодера для PAC-кодов
2024-06-20
SCID: 54.1/wa9aqjzv
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SIMD parallelization (NEON, SSE, AVX256)fast list decoderfour-node fast list (FFL) decoding algorithmpolarization-adjusted convolutional (PAC) codessoftware high-throughput decoder
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Abstract (AI)
In this letter, a novel high throughput software polarization-adjusted convolutional (PAC) decoder based on the four-node fast list (FFL) decoding algorithm is proposed. To improve the parallel processing capabilities of the proposed decoder, we effectively parallel map the FFL decoding algorithm to processors by using the single-instruction-multiple-data (SIMD) instruction set to decode multiple frames of data in parallel. Moreover, the proposed decoder has sufficient generality to be implemented on X86 and ARM processors (NEON, SSE, and AVX256 instruction sets). Experimentations show that the proposed software PAC decoder can achieve 26.256 Mb/s.
Key Findings
1
A novel high-throughput software PAC decoder based on the four-node fast list (FFL) decoding algorithm is proposed.
2
Experimental results show the proposed software PAC decoder achieves a throughput of 26.256 Mb/s.
3
The decoder maps the FFL algorithm to processors using SIMD to decode multiple frames in parallel, improving parallel processing capabilities.
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The implementation is general enough to run on x86 and ARM processors, supporting NEON, SSE, and AVX256 instruction sets.
Research Object
Software implementation of a fast list decoder for polarization-adjusted convolutional (PAC) codes
Research Subject
High-throughput, parallel SIMD-mapped performance and portability of the four-node fast list (FFL) PAC decoding algorithm on x86 and ARM (NEON, SSE, AVX256) processors, including achieved throughput
Publication Details
Publication Date
2024-06-20
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