Comparative Analysis 6T, 8T and 10T SRAM in CMOS and FinFET Technologies: A Review

Static Random-Access Memory (SRAM) plays a pivotal role in modern integrated circuits, serving as a critical component for data storage and fast data access. This review paper provides a comprehensive examination of SRAM cells, focusing on their implementation in two prominent semiconductor technologies: Complementary Metal-Oxide-Semiconductor (CMOS) and FinFET. The performance parameter analysis of the various SRAM design configurations i.e., 6T, 8T and 10T SRAM and challenges encountered in CMOS technology, highlighting key parameters such as speed, power consumption, and stability. Radiation hardness is a critical attribute for SRAM (Static Random-Access Memory) in mission-critical and radiation-prone applications due to the potential adverse effects of ionizing radiation on electronic devices like Single Event Upset (SEU) error occurring in SRAM. The resilience to radiation-induced errors is of paramount importance in the SRAM. An effort is made to compare the radiation hardness of CMOS and FinFET based SRAM architecture. This research lays emphasis on the selection of an optimal SRAM cell design, whether 6T, 8T, or 10T in CMOS or FinFET technology depends on the specific application requirements, balancing tradeoffs between area, efficiency, performance metrics, and resilience to radiation-induced faults. It also establishes the superiority of FinFET technology compared to the CMOS technology which suffers from Short Channel Effect at lower technology nodes. Further research and advancements in semiconductor technology hold the potential to refine these SRAM cell designs, addressing the evolving demands of future memory systems in both terrestrial and space environments.