Experimental demonstration of reservoir computing on a silicon photonics chip

In today’s age, companies employ machine learning to extract information from large quantities of data. One of those techniques, reservoir computing (RC), is a decade old and has achieved state-of-the-art performance for processing sequential data. Dedicated hardware realizations of RC could enable speed gains and power savings. Here we propose the first integrated passive silicon photonics reservoir. We demonstrate experimentally and through simulations that, thanks to the RC paradigm, this generic chip can be used to perform arbitrary Boolean logic operations with memory as well as 5-bit header recognition up to 12.5 Gbit s−1, without power consumption in the reservoir. It can also perform isolated spoken digit recognition. Our realization exploits optical phase for computing. It is scalable to larger networks and much higher bitrates, up to speeds >100 Gbit s−1. These results pave the way for the application of integrated photonic RC for a wide range of applications. Reservoir computing uses computational techniques related to neural networks to perform certain computing tasks. Here, the authors implement a passive optical reservoir computing scheme integrated on a silicon chip, operating at speeds up to 12.5 Gbit s−1.